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semiconductor group 1 1.96 ? 4 194 304 words by 4-bit organization ? 0 to 70 c operating temperature ? performance: ? single + 5 v ( 10 %) supply ? low power dissipation max. 550 mw active (hyb5116405bj/bt-50) max. 495 mw active (hyb5116405bj/bt-60) max. 440 mw active (hyb5116405bj/bt-70) max. 660 mw active (hyb5117405bj/bt-50) max. 605 mw active (hyb5117405bj/bt-60) max. 550 mw active (hyb5117405bj/bt-70) 11 mw standby (ttl) 5.5. mw standby (mos) ? output unlatched at cycle end allows two-dimensional chip selection ? read, write, read-modify-write, cas -before-ras refresh, ras -only refresh, hidden refresh, self refresh and test mode ? hyper page mode (edo) capability ? all inputs, outputs and clocks fully ttl-compatible ? 4096 refresh cycles / 64 ms for hyb5116405bj/bt (4k-refresh) ? 2048 refresh cycles / 32 ms for hyb5117405bj/bt (2k-refresh) ? plastic package: p-soj-26/24 300 mil p tsopii-26/24 300 mil -50 -60 -70 t rac ras access time 50 60 70 ns t cac cas access time 13 15 20 ns t aa access time from address 25 30 35 ns t rc read/write cycle time 84 104 124 ns t hpc hyper page mode (edo) cycle time 20 25 30 ns hyb5116405bj/bt -50/-60/-70 hyb5117405bj/bt -50/-60/-70 4m x 4-bit dynamic ram 2k & 4k refresh (hyper page mode- edo) advanced information
semiconductor group 2 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram the hyb 5116(7)405bj/bt is a 16mbit dynamic ram organized as 4194304 words by 4-bits. the hyb 5116(7)405bj/bt utilizes a submicron cmos silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. multiplexed address inputs permit the hyb 5116(7)405bj/bt to be packaged in a standard soj 26/24 or tsopii-26/24 plastic package, both with 300 mil width. these packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. system-oriented features include single + 5 v ( 10 %) power supply, direct interfacing with high-performance logic device families such as schottky ttl. ordering information pin names type ordering code package descriptions hyb 5116405bj-50 q67100-q1098 p-soj-26/24 300 mil dram (access time 50 ns) hyb 5116405bj-60 q67100-q1099 p-soj-26/24 300 mil dram (access time 60 ns) hyb 5116405bj-70 q67100-q1100 p-soj-26/24 300 mil dram (access time 70 ns) hyb 5116405bt-50 on request p-tsopii-26/24 300mil dram (access time 50 ns) hyb 5116405bt-60 on request p-tsopii-26/24 300mil dram (access time 60 ns) hyb 5116405bt-70 on request p-tsopii-26/24 300mil dram (access time 70 ns) hyb 5117405bj-50 q67100-q1101 p-soj-26/24 300 mil dram (access time 50 ns) hyb 5117405bj-60 q67100-q1102 p-soj-26/24 300 mil dram (access time 60 ns) hyb 5117405bj-70 q67100-q1103 p-soj-26/24 300 mil dram (access time 70 ns) hyb 5117405bt-50 on request p-tsopii-26/24 300mil dram (access time 50 ns) hyb 5117405bt-60 on request p-tsopii-26/24 300mil dram (access time 60 ns) hyb 5117405bt-70 on request p-tsopii-26/24 300mil dram (access time 70 ns) a0-a11 row address inputs for hyb5116405 a0-a9 column address inputs for hyb5116405 a0-a10 row and column address inputs for hyb5117405 ras row address strobe oe output enable i/o1-i/o4 data input/output cas column address strobe we read/write input v cc power supply (+ 5 v) v ss ground (0 v) n.c. not connected
semiconductor group 3 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram pin configuration p-soj-26/24 300 mil p-tsopii-26/24 300 mil vcc i/o1 i/o2 we ras a11 a10 a0 a1 a2 a3 vcc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 vss i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 vss vcc i/o1 i/o2 we ras nc a10 a0 a1 a2 a3 vcc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 vss i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 vss hyb 5116405 bj/bt hyb 5117405 bj/bt
semiconductor group 4 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram block diagram for hyb 5116405 no. 2 clock generator column address buffer(10) refresh controller refresh counter (12) address buffers(12) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 4096x1024x4 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we cas 4096 1024 x4 . ras 10 12 10 4 4 4 i/o1 i/o2 i/o3 i/o4 oe 12 12 a10 a11 voltage down generator vcc vcc (internal)
semiconductor group 5 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram block diagram for hyb 5117405 no. 2 clock generator column address buffer(11) refresh controller refresh counter (11) address buffers(11) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 2048x2048x4 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we cas 2048 2048 x4 . ras 11 11 11 4 4 4 i/o1 i/o2 i/o3 i/o4 oe 11 11 a10 voltage down generator vcc vcc (internal)
semiconductor group 6 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram absolute maximum ratings operating temperature range ............................................................................................0 to 70 c storage temperature range.........................................................................................C 55 to 150 c input/output voltage ................................................................................-0.5 to min (vcc+0.5,7.0) v power supply voltage...................................................................................................-1.0v to 7.0 v power dissipation.............................................................................................................. ....... 1.0 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics( note : values in brackets for hyb 5117405 bj/bt) t a = 0 to 70 c, v ss = 0 v, v cc = 5 v 10 %; t t = 2 ns parameter symbol limit values unit test condition min. max. input high voltage v ih 2.4 vcc+0.5 v 1) input low voltage v il C 0.5 0.8 v 1) output high voltage ( i out = C 5 ma) v oh 2.4 C v 1) output low voltage ( i out = 4.2 ma) v ol C0.4v 1) input leakage current (0 v v ih vcc + 0.3v, all other pins = 0 v) i i(l) C 10 10 m a 1) output leakage current (do is disabled, 0 v v out vcc + 0.3v) i o(l) C 10 10 m a 1) average v cc supply current: -50 ns version -60 ns version -70 ns version (ras , cas , address cycling: t rc = t rc min.) i cc1 C C C 100(120) 90 (110) 80 (100) ma ma ma 2) 3) 4) 2) 3) 4) 2) 3) 4) standby v cc supply current (ras =cas = v ih ) i cc2 C2maC average v cc supply current, during ras -only refresh cycles: -50 ns version -60 ns version -70 ns version (ras cycling, cas = v ih , t rc = t rc min.) i cc3 C C C 100(120) 90 (110) 80 (100) ma ma ma 2) 4) 2) 4) 2) 4)
semiconductor group 7 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram average v cc s u p p l y c u r r e n t , during hyper page mode: -50 ns version -60 ns version -70 ns version (ras = v il , cas , address cycling: t pc = t pc min.) i cc4 C C C 70 (70) 55 (55) 45 (45) ma ma ma 2) 3) 4) 2) 3) 4) 2) 3) 4) standby v cc supply current (ras = cas = v cc C 0.2 v) i cc5 C1ma 1) average v cc supply current, during cas - before-ras refresh mode: -50 ns version -60 ns version -70 ns version (ras , cas cycling: t rc = t rc min.) i cc6 C C C 100(120) 90 (110) 80 (100) ma ma ma 2) 4) 2) 4) 2) 4) average self refresh current (cbr cycle with tras>trassmin., cas held low, we =vcc-0.2v, address and din=vcc - 0.2v or 0.2v) i cc7 _1ma capacitance t a = 0 to 70 c, v cc = 5 v 10 %, f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a10,a11) c i1 C5pf input capacitance (ras , cas , we , oe ) c i2 C7pf i/o capacitance (i/o1-i/o4) c io C7pf dc characteristics( note : values in brackets for hyb 5117405 bj/bt) t a = 0 to 70 c, v ss = 0 v, v cc = 5 v 10 %; t t = 2 ns parameter symbol limit values unit test condition min. max.
semiconductor group 8 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram ac characteristics 5)6) 16e t a = 0 to 70 c, v cc = 5 v 10 %, t t = 2 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max. common parameters random read or write cycle time t rc 84 C 104 C 124 C ns ras precharge time t rp 30 C 40 C 50 C ns ras pulse width t ras 50 10k 60 10k 70 10k ns cas pulse width t cas 8 10k 10 10k 12 10k ns row address setup time t asr 0C0C0Cns row address hold time t rah 8C10C10Cns column address setup time t asc 0C0C0Cns column address hold time t cah 8C10C12Cns ras to cas delay time t rcd 12 37 14 45 14 53 ns ras to column address delay t rad 10 25 12 30 12 35 ns ras hold time t rsh 13 15 C 17 C ns cas hold time t csh 40 50 C 60 C ns cas to ras precharge time t crp 5C5C5Cns transition time (rise and fall) t t 150150150ns7 refresh period for hyb5116405 t ref C64C64C64ms refresh period for hyb5117405 t ref C32C32C32ms read cycle access time from ras t rac C50C60C70ns8, 9 access time from cas t cac C13C15C17ns8, 9 access time from column address t aa C25C30C35ns8,10 oe access time t oea C13C15C17ns column address to ras lead time t ral 25 C 30 C 35 C ns read command setup time t rcs 0C0C0Cns read command hold time t rch 0C0C0Cns11 read command hold time referenced to ras t rrh 0C0C0Cns11 cas to output in low-z t clz 0C0C0Cns8 output buffer turn-off delay t off 013015017ns12
semiconductor group 9 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram output turn-off delay from oe t oez 013015017ns12 data to cas low delay t dzc 0C0C0Cns13 data to oe low delay t dzo 0C0C0Cns13 cas high to data delay t cdd 10 C 13 C 15 C ns 14 oe high to data delay t odd 10 C 13 C 15 C ns 14 write cycle write command hold time t wch 8C10C10Cns write command pulse width t wp 8C10C10Cns write command setup time t wcs 0C0C0Cns15 write command to ras lead time t rwl 13 C 15 C 17 C ns write command to cas lead time t cwl 13 C 15 C 17 C ns data setup time t ds 0C0C0Cns16 data hold time t dh 8C10C12Cns16 read-modify-write cycle read-write cycle time t rwc 113 C 138 C 162 C ns ras to we delay time t rwd 64 C 77 C 89 C ns 15 cas to we delay time t cwd 27 C 32 C 36 C ns 15 column address to we delay time t awd 39 C 47 C 54 C ns 15 oe command hold time t oeh 10 C 13 C 15 C ns hyper page mode (edo) cycle hyper page mode (edo) cycle time t hpc 20 C 25 C 30 C ns cas precharge time t cp 8C10C10Cns access time from cas precharge t cpa C27C32C37ns7 output data hold time t coh 5C5C5Cns ras pulse width in edo mode t ras 50 200k 60 200k 70 200k ns cas precharge to ras delay t rhpc 27 C 32 C 37 C ns ac characteristics (contd) 5)6) 16e t a = 0 to 70 c, v cc = 5 v 10 %, t t = 2 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 10 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram hyper page mode (edo) read-modify-write cycle hyper page mode (edo) read- write cycle time t prwc 58 C 68 C 77 C ns cas precharge to we t cpwd 41 C 49 C 56 C ns cas -before-ras refresh cycle cas setup time t csr 10 C 10 C 10 C ns cas hold time t chr 10 C 10 C 10 C ns ras to cas precharge time t rpc 5C5C5Cns write to ras precharge time t wrp 10 C 10 C 10 C ns write hold time referenced to ras t wrh 10 C 10 C 10 C ns cas -before-ras counter test cycle cas precharge time t cpt 35 C 40 C 40 C ns self refresh cycle ras pulse width t rass 100k _ 100k _ 100k _ ns 17 ras precharge t rps 95 _ 110 _ 130 _ ns 17 cas hold time t chs -50 _ -50 _ -50 _ ns 17 test mode write command setup time t wts 10 C 10 C 10 C ns write command hold time t wth 10 C 10 C 10 C ns cas hold time t chrt 30 C 30 C 30 C ns ac characteristics (contd) 5)6) 16e t a = 0 to 70 c, v cc = 5 v 10 %, t t = 2 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 11 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram notes: 1) all voltages are referenced to v ss . 2) i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 3) i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 4) address can be changed once or less while ras = vil. in case of icc4 it can be changed once or less during a hyper page mode (edo) cycle 5) an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume t t = 2 ns. 7) v i h (min.) and v i l (max.) are reference levels for measuring timing of input signals. transition times are also measured between v i h and v i l . 8) measured with the specified current load and 100 pf at vol = 0.8 v and voh = 2.0 v. access time is determined by the latter of t rac , t cac , t aa ,t cpa , t oea . t cac is measured from tristate. 9) operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10) operation within the t rad (max. ) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11) either t rch or t rrh must be satisfied for a read cycle. 12) t off (max.) , t oez (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. t off is referenced from the rising edge of ras or cas , whichever occurs last. 13) either t dzc or t dzo must be satisfied. 14) either t cdd or t odd must be satisfied. 15) t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.) , t cwd > t cwd (min.) and t awd > t awd (min.) , the cycle is a read-write cycle and i/o will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of i/o (at access time) is indeterminate. 16) these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles. 17)when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refreshed on an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediately after exit from self refresh. if row addresses are being refreshed in any other manner (ror - distributed/burst; or cbr-burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from self refresh
semiconductor group 12 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram read cycle row column row valid data out ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z h or l wl1
semiconductor group 13 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram write cycle (early write) ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column row row t rah t wcs h or l wl2
semiconductor group 14 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram write cycle (oe controlled write) valid data t rwl t wp t oeh t odd t cwl t dzo t oea t clz t ds t oez t dh t rc v ih v il row t dzc h or l hi-z hi-z column row t asc t rad t ral t cah t rah ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr wl3
semiconductor group 15 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram read-write (read-modify-write) cycle row row t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il t asr column t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac h or l t asc v ih v il v ih v il ras cas address v ih v il wl4
semiconductor group 16 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram hyper page mode (edo) read cycle t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t csh t cas t rcd t rah t asr column 2 row data out ras i/o we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol oe t ras t crp t asc t hpc t cah t rad t rhcp t asc t rcs t rrh t rch (output) t rac t aa t cac t clz t oea t oes t coh t cac t aa t cpa data out column n column 1 data out t oez t off t cac t aa t cpa 1 2 t coh n wl5
semiconductor group 17 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram hyper page mode (edo) early write cycle t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t cwl t wcs t wp t wch t csh t cas t rcd t rah t asr t dh t ds t dh t ds column 1 column 2 row addr data in n data in 2 data in 1 column n ras i/o (input) we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol oe t ras t crp t asc t cwl t wcs t wp t wch t cwl t wcs t wp t wch t rwl t dh t ds t hpc t cah t rad t rhcp t asc wl8
semiconductor group 18 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram hyper page mode (edo) late write and read-modify write cycle t cah t cp t dzc t dzo t rac t cac t clz t rcs t aa t oea t rcd t rad t rah t asr t asc t cas t cas t prwc t cwd t cah t asc t cas t rsh t rp t crp t asr t cah t asc t ral t cwd t rwd t cwl t cwl t cwd t awd t awd t wp t wp t cwl t rwl t awd t wp t odd t oeh t dh t ds t cpa t oez t clz t dzc t aa t cac t oea t ds t oez t dh t oeh t aa t odd t dzc t cpa t oea t clz t ds t dh t oeh t odd ras v ih v il cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol we oe address i/o (inputs) i/o (outputs) data in data in data in data out out data data out row column column row t rasp t csh column t cpwd t cpwd wl17
semiconductor group 19 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram ras -only refresh cycle t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row row hi-z address ras cas i/o (outputs) h or l wl9
semiconductor group 20 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram cas -before-ras refresh cycle t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o (outputs) i/o (inputs) oe we cas v oh v ol wl10
semiconductor group 21 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram hidden refresh cycle (read) ras i/o (outputs) i/o (inputs) oe we address cas t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh h or l valid data out row column row hi-z v oh v ol wl11
semiconductor group 22 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram hidden refresh cycle (early write) ras i/o (output) i/o (input) we address v ih v il v ih v il v ih v il cas v ih v il v ih v il h or l t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc row row valid data hi-z column v oh v ol t wrp t wrh wl12
semiconductor group 23 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram cas before ras self refresh cycle t rps t rass t rp t crp t cp t rpc t wrh t wrp t csr t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o (outputs) i/o (inputs) oe we cas v oh v ol t chs wl13
semiconductor group 24 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram cas -before-ras refresh counter test cycle t csr t asr t asc t chr t cp t wrp t ral t cah t rsh t rp t ras t cas t rcs t cdd t cac t aa t wrh t oea t odd t clz t dzc t dzo t oez t off t rwl t cwl t wch t wcs t wrh t wrp t ds t dh v ih v il v ih v il v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras i/o (inputs) oe we address cas i/o (outputs) i/o (outputs) i/o (inputs) we oe column row data out data in hi-z read cycle: write cycle: t rrh t rch
semiconductor group 25 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram test mode entry t rc t ras t rp t rpc t crp t chr t wth t rpc t rp t cp t csr t wts t cdd t off t oez t odd i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il cas ras v ih v il v ih v il h or l hi-z address t rah t asr v ih v il row wl15 hi-z
semiconductor group 26 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram test mode as the hyb 5116(7)405bj/bt is organized internally as 1m x 16-bits, a test mode cycle using 4:1 compression can be used to improve test time. note that in the 4m x 4 version the test time is reduced by 1/4 for a n test pattern. in a test mode write the data from each i/o pin is written into four 1m blocks simultaneously (all 1 s or all 0 s). in test mode read each i/o output is used for indicating the test mode result. if the internal four bits are equal, the i/o would indicate a 1. if they were not equal, the i/o would indicate a 0. the wcbr cycle (we , cas before ras ) puts the device into test mode. to exit from test mode, a cas before ras refresh, ras only refresh or hidden refresh can be used.refresh during test mode operation can be performed by normal read cycles or by wcbr refresh cycles. row addresses a0 through a9 have to kept high to perform a testmode entry cycle. all other addresses are dont care.
semiconductor group 27 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram block diagram in test mode normal test vcc vss i/o 3 normal test vcc vss i/o 2 normal test vcc vss i/o 1 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block i/o 4 i/o 3 i/o 2 i/o 1 normal test normal normal normal test test test a0c,a1c a0c,a1c a0c,a1c a0c,a1c a0c,a1c a0c,a1c a0c,a1c a0c,a1c normal test vcc vss i/o 4
semiconductor group 28 hyb5116(7)405bj/bt-50/-60/-70 4m x 4-edo dram package outlines plastic package p-tsopii-26/24 (300mil) (thin small outline package, smd) 1) does not include plastic or metal protrusion of 0.15 max. per side 24x 0.2 m -0.1 -0.2 0.6 0.1 1) index marking 9.22 13 1 14 26 7.62 +0.12 0.4 1.27 17.27 0.2 - + 0.13 - + -0.25 gpx05857 gpj05628

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